In the very begining, i want to use cpld to control dds output a sine wave. However, i tried both SPI and parallel method, it output nothing. So i decide to check the problem step by step. Here goes my question. When i just input a 25Mhz clock and master reset ad9914, I found nothing in sync_clk pin. When i use direct mode to output a 10Mhz, i found sync_clk output a clock whose duty cycle is wierd. so i'm confused how to make sync_clk work right, because i think some basic configuration should setup based on it.