Hello, Could you please help to provide the AD9364 HDL sample code and the IIO oscilloscope user guider? Thank you very much.
Do the following:
assign adc_r1_mode = 1'b1;
Repeat the same for DAC:
After synthesis - look at your log file and you should see all the logic related to the other two channels optimized out.
Please start looking here:
AD-FMCOMMS4-EBZ User Guide [Analog Devices Wiki]
Thanks. Since the AD9364 is 1T/1R, do we have the 1T/1R code? The link just show the information how to use AD9361 board to work well in Zedboard, however we cannot tell how to get the optimized code to use AD9364 which is just 1T/1R rather than AD9361 2T/2R.
AD9361/64 uses the same SW device driver and HDL core.
The only difference is the configuration.
To tell the kernel which device you are using you have to prepare the SD Card.
See here: http://wiki.analog.com/resources/tools-software/linux-software/zynq_images#preparing_the_image
It’s also a good idea to update your tools and boot files.
Thanks. The AD9361/4 use the same HDL code, however that might make trouble to optimize the HDL code size into the FPGA.We want to use 1T/1R AD9364 instead of applying the current AD9361 HDL code which the size is bigger than optimized AD9364. Therefore the question is whether you could help to modify the current AD9361 HDL code to make a smaller one which is dedicated for AD9364.
moved to FPGA reference designs.
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