I am using ADSP-BF537 with 182 pin package.
As the processor mentioned is supporting Max 4MB, my requirement is to interface 64MB of flash using AMS0 and AMS1 only.
The other two bank select pins AMS2 and AMS3, I want use them for other purposes like for memory devices and peripheral.
Currently I have implemented the schematic for 8MB flash in the following manner.
1. I have connected the address lines A1-A19 of processor to A0-A18 of flash, D0-D15 of processor to D0-D15 of flash
2. The remaining address line A19, A20, A21, I have connected to GPIOs PF4, PF5, PG13
3. AMS0 and AMS1 are ANDed and the out put is connected to nCS of the flash.
Whether my implementation is correct?
Please correct me if I am wrong.
Thank you very much for the support in advance.