On the datasheet,
fSCLK is 32MHz(max), it means the time of 1 cycle is 31.25nSec.
On the other hand, t4(Data access time after SCLK falling edge) is 36nSec(max).
I think that t4 is longer than the cycle of fSCLK(max) is a problem.
For this matter, it would be nice if you could explain about detail.