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AD7266 Data access time

Question asked by y_kawabata@adm.co.jp on Jul 17, 2014
Latest reply on Aug 28, 2014 by KarenNE

Hi,

 

On the datasheet,

fSCLK is 32MHz(max), it means the time of 1 cycle is 31.25nSec.

On the other hand, t4(Data access time after SCLK falling edge) is 36nSec(max).

I think that t4 is longer than the cycle of fSCLK(max) is a problem.

For this matter, it would be nice if you could explain about detail.


Best Regards,

yk

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