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ADuC7126 Pin P4.5 behavior when JTAG is connected

Question asked by Igor_K on Jul 17, 2014
Latest reply on Aug 12, 2014 by ABuda


I ported our code from ADuC7026 into ADuC7126 and see difference in Port 4 pin 5 behavior WHEN JTAG IS CONNECTED:

On ADuC7026 it is regular GPIO (mode 00),

on ADuC7126 it is GPIO/RCLK (return clock to JTAG) in the same mode 00.

My code uses this port pin as GPIO which controls some analog switch, and it always should be stable: either 0 or 1 (quasi-static), changes only by user command which happens very seldom. Unfortunately, I cannot change this pin to some other one.

When JTAG is connected for debugging, the JTAG pulses are present on this pin, which my application cannot tolerate.

I use ULINK-2 emulator for both ADuC 7026 and 7126, and do not use RCLK signal because 7026 does not have it, and 7126 works fine with emulator without it.

According to Data Sheet Rev C page 58, this RCLK signal appears in mode 00. I tried to stop program and manually set this pin mode to 01,10,11 modes - when processor runs again, it always show RCLK pulses, in all modes.

QUESTION: is here any way do disable RCLK functionality of this pin when emulator is connected?