I test my AD9957 board to generate a tone(example: 239.2MHz) in one tone mode, but find an unwanted tone (example:276.896MHz), the center of these 2 tone is (system_CLK)/2 (516.096MHz). The unwanted tone is too close to the signal, and I can't filter it out. The PLL is locked (PLL_lock is high). I try another freq like 174.928MHz, the result is the same.
I'll use AD9957 to transmit DAB signal and my Data sampling rate is 2.048MHz(I or Q), so I can't select a higher system_CLK.
Is there any wrong setting or design in the board? Thank you.
my parameter setting is :
reference clock=24.576MHz, PLL multiplier=21
CCI Interpolation rate=63
PDCLK=2.048MHz, PDCLK rate control enable.
data samples rate=2.048MHz
attach files are.
(1)schematics of the ad9957 board (2)spectrum of generating 209.936MHz (3)spectrum of generating174.928MHz
my register setting:
Profile0(0x0E): 239.2MHz: 0xFC,0xB5,0x00,0x00,0x76,0xA6,0x9A,0x6A
Profile0(0x0E): 174.928MHz: 0xFC,0xB5,0x00,0x00,0x56,0xC5,0x14,0x51