I am evaluating VisualDSP++ and using cycle_count library. I am wondering if there is a way to differentiate cycles spend to get the data in memory than the ones used to compute ?
Thanks for your help.
Unfortunately this is not possible.
Thanks for your answer Craig.
When running VisualDSP++ on simulator mode and using cycle_count library, does the memory accesses take into account where the data is located ?
Said differently, can I see differences in the cycle count if I read a data in SDRAM (for exemple) then elsewhere ?
The Cycle Accurate Simulator model some latencies associated with external memory accesses, such as those associated with back to back load/store operations, however the simulator does not provide a cycle-accurate model of external memory.
If you compare cycle counts for code that relies heavily on external memory accesses, or peripheral bus activity, you would find that the cycle counts differ between the Simulator and Hardware.
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