I work with on AD9361(FMCOMMS2) with my XILINX-V6 board.
I make it work on FDD mode and the REF_CLK is 40MHz, and the working frequency is 2.45GHz. I follow the instructions of the AD9361_Design_File_Package to configure the chip, the problem is as follows:
During my initialzation, I first enter the chip into ALERT state with FDD mode. BBPLL VCO calibration and RF synthesizer charge pump calibration is done. Then I configure the RF related registers(based on LUT form ADI) and follow the order to triger the RF synthesizer VCO calibraion, BUT the PLL lock bit in register 0x287 donot go high to indicate the calibration is done.
I re-check my settings twice to confirm my HDL code agrees with the PDF saying.
And I also notice that the lock detector 0x28A has a lock detect count setting. I let this time to be maximum as 2048 reference clock time. After calculating, this time is still less than my calculated VCO calibtation time.
Is that the reason why I couldnot detect the PLL lock state ?
What other methods can I know the PLL is lock ? Or
whar other methods can I check sth is wrong with my design ?