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AD 9246 Evaluation Board HSC-ADC-EVALB-DCZ

Question asked by erinsb on Jul 11, 2014
Latest reply on Jul 15, 2014 by TonyM

Hi there,

 

I am currently having some difficulty in reading the signals from the AD9246 evaluation board HSC-ADC-EVALB-DCZ.  I am using ADCAnalyzer, along with SPIController, and I can’t seem to get a clear signal that matches what I am giving to the board as an analog input. I’ve provided below a walk-through of my setup and the corresponding results.  I would greatly appreciate any input regarding any mistakes I might be making, or any suggestions you might have.

 

For the whole set-up shown here, (except where noted,) I am using a wave generator to create a sine clock signal with a 20MHz frequency, and 2.8Vpp.  The analog input is a sine wave, set at 100kHz and 1.70Vpp.

 

The input of the analog signal, to the board looks like:

This wave has a roughly 800mVpp, compared to the 1.70Vpp waveform being generated.

 

Signal from wave generator to board.jpg

 

 

The signals shown below are the Vin+ and Vin- pins. They fall within the 2Vpp range that is given in the datasheet.

 

Vin+.jpg

Vin+.jpg

The following captures are, (from top to bottom): D13 (MSB), D11, D0 (LSB)

All of these signals are in sync with the Vin+/Vin- signal.

D13.jpg

D11.jpg

D0.jpg

When I try to capture the wave signal using ADCAnalyzer, I get the following image:

AD9246_1p70Vpp.PNG

 

Zoomed in, the signal looks like:

AD9246_1p70Vpp_Hzoom.PNG

 

While this is a periodic signal, it doesn’t resemble a sine wave.

 

Also, the Logic Analyzer and the Bus Check are shown below.  It seems that the first 4 bits should be switching, although I’m not really sure how to make them switch, if they aren’t already switching.  There also seems to be some inconsistancy in the frequency at which each of the bits 4-13 are switching.  In particular, if you compare D13 (MSB) from the pinout on the FPGA board (see signal above) to the image below, you'll notice that the signal output has a 50% duty cycle, compared to the much lower duty cycle being shown below.  It's a little difficult to read, but D13 is the topmost row of logic data being shown below.


BusCheck_LogicAnalyzer.PNG

(When using a 1.00Vpp signal, still at 100kHz frequency, I get the following signal):

AD9246_1p0Vpp.PNG

 

I used the standard Configuration File for AD9246, with the following shown settings:

 

 

 

SPI_Controller.PNGFFTConfig.PNG

 

Please let me know if you have any questions, or would like more details regarding the set-up and corresponding signals.  We aren’t exactly sure how to proceed, and any help or input you could give us would be greatly appreciated.

 

Thanks,

Erin

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