I have connected the ADV7611 chip LLC clock output to ADV7343 chip CLKIN_A pin.
The ADV7343 chip maximum clock in frequency is 80MHz but the ADV7611 supports 13.5MHz to 165MHz.
The ADV7611 chip output frequency is based on the input video.
If the input video is UXGA means what is the output frequency, if output frequency exceeds 80MHz what i have to do?
Shall i control the output frequency by DR_STR_CLK[1:0], IO, Address 0x14[3:2] => 01 (Medium low (2×) for LLC up to 60 MHz).
Kindly suggest this design approach.