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AD9958 Datasheet ambiguity - Power down modes

Question asked by Ant1882 on Jul 9, 2014
Latest reply on Jul 10, 2014 by Ant1882



On page 21 of the AD9958 datasheet, power-down functions, there seems to be some ambiguity about when the power down pins of the CFR[7:6] are active. Firstly it states:


"When the input pin, PWR_DWN_CTL, is high, the AD9958 enters a power-down mode based on the FR1[6] bit. When the PWR_DWN_CTL input pin is low, the external power-down control is inactive."


It then goes on to say:


"When the PWR_DWN_CTL input pin is high, the individual power-down bits (CFR[7:6]) and (FR1[7]) are invalid (don’t care) and unused. When the PWR_DWN_CTL input pin is low, the individual power-down bits control the power-down modes of operation."


In the description of FR1 on page 40 it states the former case. Could someone confirm this is correct? that PWR_DWN_CTL should be set high in order to allow setting the power down modes?


Best Regards