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Question asked by on Jul 7, 2014
Latest reply on Jul 23, 2014 by DougI

Please teach me about AD9681-SYNC PIN.



The following description is in the data sheet.

Rev. A | Page 22 of 40

The AD9681 clock divider can be synchronized using the external SYNC input.

Bit 0 and Bit 1 of Register 0x109 allow the clock divider to be resynchronized on every SYNC signal or only on the first SYNC signal after the register is written.

A valid SYNC causes the clock divider to reset to its initial state.

This synchro-nization feature allows the clock dividers of multiple devices to be aligned to guarantee simultaneous input sampling.


Do not it synchronize even if SYNC PIN is not input because the same clock is used?

It is being written that it is necessary for being synchronous in the data sheet.

Please teach why it to be necessary kindly.



Please teach me about SYNC Input Timing Requirements.

There is a description in the following data sheet P8 /Table 5.

SYNC to rising edge of CLK+ setup time : 0.24 (Limit) ns  typ

SYNC to rising edge of CLK+ hold time : 0.40 (Limit) ns  typ.

Is the above-mentioned a mistake of minimum value?

I do not understand this time regulations.



Please teach me about SYNC Input Timing Requirements.

Should I rise up SYNC PIN at the time of each sampling ADC?

When paraphrasing it , Do CLK + and SYNC become signals of the same wavelength?


Thank you.