# Maximal rate for serial communications with AD9681

Question asked by kotoo@fujiele.co.jp on Jul 7, 2014
Latest reply on Jul 10, 2014 by DougI

1).

The following description is in the data sheet.

Rev. A | Page 26 of 40

Data from each ADC is serialized and provided on a separate channel in two lanes in DDR mode.

The data rate for each serial stream is equal to 16 bits times the sample clock rate,

with amaximum of 500 Mbps/lane [(16 bits*125 MSPS)/(2 × 2) =500 Mbps/lane)].

The lowest typical conversion rate is 10 MSPS.

See the Memory Map section for details on enabling this feature.

I think as follows.

The data rate : 16 bits*125 MSPS=2Gsps.

The lane data rate : 2Gbps/2=1Gbps/lane

The sample clock rate : 2Gbps/2lane/2=500MHz.

Could you teach the above-mentioned?

2).

Please teach in relation to the question on 1).

When using it by the following setting, how many is the LVDS maximum clock of ANSI-644 of 1Lane?

Figure 8. Wordwise DDR, One-Lane, 1× Frame, 12-Bit Output Mode

Do you support it to following 750MHz?

12bit*125M/2=750MHz

Thank you.