I want to know that what BBPLL locking time and its resolution.
In my application i have to change sampling rates frequently so i have doubt on locking time. with how much its freq can stable.
thanks for support in advance.
BBPLL works over a 715MHz-1430MHz range. Resolution depends on the reference frequency used.
The block diagram below and the formulas on pg 20 of AD9361 Register Map Reference Manual should provide you with enough information to calculate output frequency and determine resolution for a given reference frequency.
See below an example of commonly used data rates than can be achieved.
Sample Rate (MSPS)
do you solved this problem? Im faced this problem too. BBPLL lock bit doesnt set in 1 (register 0xE5 7bit =0).
Are you using ADI provided device drivers?
Please find the drivers at the link below:
How you are configuring AD9361?
My project contain the FPGA, which includes spi controller and PC program on C++. I can read and write register value on PC program through the com port with FPGA. All of the code for the initialization AD9361 is running on PC. I got dev_dbg log from the demo project and mine. They are very different. Although I tried to save the sequence of commands in the my project. I have now a problem in the registers 247 and 287. In the demo project, they have a value of 0x2. In my project, they have a value of 0x0.
I don't know how to configure axi (dac and adc). How i can init dac and adc? How values i have write in registers?
Value of 0x02 in register 247 and 248 means that PLLs are locked, Tx and Rx. I you get 0x00, it means that the PLLs are not locked and that some part of your configuration is not correct.
I would suggest reading AD9361 Reference Manual (available for download on our website) to determine which functions to use to configure different blocks of the IC. For example, Rx ADC setup is covered on page 11. The function to use is ad9361_set_rx_rf_bandwidth function.
If you have further question on driver use, please post your question in Microcontroller no-OS Drivers.
Thank you, till.
Can you give me the link on this document?
AD9361 AND AD9364 INTEGRATED RF AGILE TRANSCEIVER DESIGN RESOURCES | Analog Devices
This is the link. Download requires registration.
Thank you, till!
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