I would like to design a transaction module between FPGA and TS201 under pipeline mode. I need to use a FIFO strategy and set ACK as the signal of handshaking cause there are some timing differences between DSP and FPGA. Now I'm confusing at the timing logic with different pipeline depth. Let's take DSP READ operation as an example, ACK is pulled down by FPGA when FPGA's FIFO is empty, after some wait cycles, ACK is pulled up by FPGA as soon as the data is ready, then the DSP begine to read from FPGA. Could you please show me the timing logic diagram under this conditon with different pipeline depth(1,2,3,4)?