I require some advise regarding the usage and operation of the AD9102 device.
I am using the AD9102 to output a pattern straight from the SRAM memory (DDS not used). This pattern does not repeat (i.e. the DAC_REPEAT_CYCLE =1). I have also set the PAT_PERIOD register equal to the number of SRAM pattern samples, to ensure that the whole pattern is generated. When I assert the trigger, I can see that the shape of the pattern generated, matches the expected shape.
The problem I have however, is when I try to adjust the duration of the pattern. According to the datasheet: "The SRAM address counter can be programmed to be incremented by CLKP/CLKN (default) or by the rising edge of the DDS MSB". I have configured the DDS to increment using the CLKP/CLKN, but when I adjust the CLKP/CLKN, I see some unexpected results. The measured duration of the pattern does not match the calculated duration:
I have 100 RAM data points, my CLKP/CLKN is set to 1MHz (period = 1µs), so I expect to see a pattern of 100µs duration, but instead the observed pattern duration is 720µs.
I would like to know:
1) Can the AD9102 device be used as described above?
2) If so, are there any special register settings?
My AD9102 registers are setup as follows:
My setup procedure is as follows:
1) The DDS is powered up
2) The registers are setup in the same order as the table above
3) I then update the SRAM with the desired pattern
4) Next I set the CLK to get the desired pattern width
5) Finally I trigger the device to generate the pattern.
Any assistance in this matter is greatly appreciated.