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AD9102: Adjusting width of arbitrary waveform

Question asked by charlm on Jul 3, 2014
Latest reply on Oct 3, 2014 by larrywelchusa

Hi,

 

I require some advise regarding the usage and operation of the AD9102 device.

 

I am using the AD9102 to output a pattern straight from the SRAM memory (DDS not used). This pattern does not repeat (i.e. the DAC_REPEAT_CYCLE =1). I have also set the PAT_PERIOD register equal to the number of SRAM pattern samples, to ensure that the whole pattern is generated. When I assert the trigger, I can see that the shape of the pattern generated, matches the expected shape.

 

The problem I have however, is when I try to adjust the duration of the pattern. According to the datasheet: "The SRAM address counter can be programmed to be incremented by CLKP/CLKN (default) or by the rising edge of the DDS MSB". I have configured the DDS to increment using the CLKP/CLKN, but when I adjust the CLKP/CLKN, I see some unexpected results. The measured duration of the pattern does not match the calculated duration:

 

I have 100 RAM data points, my CLKP/CLKN is set to 1MHz (period = 1µs), so I expect to see a pattern of 100µs duration, but instead the observed pattern duration is 720µs.

 

I would like to know:

1) Can the AD9102 device be used as described above?

2) If so, are there any special register settings?

 

My AD9102 registers are setup as follows:

   

RegisterValue
SPICONFIG0x0000
POWERCONFIG0x0000
CLOCKCONFIG0x0000
REFADJ0x0000
DACAGAIN0x0000
DACRANGE0x0000
DACRSET0x800A
CALCONFIG0x0000
COMPOFFSET0x0000
PAT_TYPE0x0001
PATTERN_DLY0x000E
DACDOF0x0000
WAV_CONFIG0x0000
PAT_TIMEBASE0x0000
PAT_PERIOD0x0064
DAC_PAT0x0001
DOUT_START_DLY0x0000
DOUT_CONFIG0x0000
DAC_CST0x0000
DAC_DGAIN0x4000
SAW_CONFIG0x0000
DDS_TW320x0000
DDS_TW10x0000
DDS_PW0x0000
TRIG_TW_SEL0x0000
DDS_CONFIG0x0001
TW_RAM_CONFIG0x0000
START_DLY0x0000
START_ADDR0x0000
STOP_ADDR0x0630
DDS_CYC0x0000
CFG_ERROR0x0000
PAT_STATUS0x0000
RAMUPDATE0x0001

 

My setup procedure is as follows:

1) The DDS is powered up

2) The registers are setup in the same order as the table above

3) I then update the SRAM with the desired pattern

4) Next I set the CLK to get the desired pattern width

5) Finally I trigger the device to generate the pattern.

 

Any assistance in this matter is greatly appreciated.

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