Hello Technical Supporting Team,
We have built our own board with four AD9915 DDS chips, but we met the following problem to synchronize all the four DDS chips.
We use an Altera FPGA to receive SYNC_OUT signal from Master DDS and distributed four synchronized SYNC_IN signals to all the four DDS chips. The synchronization procedure we followed is the “AN-1254 APPLICATION NOTE Synchronizing Multiple AD9915 DDS-Based Synthesizers”. However, we still could not synchronize all the four SYNC_CLK signals after following the 8-step procedure. After probing the SYNC_CLK with scope, we noticed that the SYNC_CLKs from DDS chips sometimes were contaminated by random spurs and had phase-jump. I assume this is the reason why the AD9915 chips could not get synchronized. Based on what we have tested so far, I have the following questions regarding to the synchronization of the AD9915 chips.
1- As it is mentioned in the Application Note, two DDS calibrations, one before setting DAC CAL and one after setting DAC CAL, need to be done in order to synchronize multi-chips. Is there any way to validate whether the calibration have been done?
2- What could be the reason of the contaminated SYNC_CLK signals I mentioned above? Do you think it can be caused by the phase mis-alignment of the SYNC_IN signal and the REF CLK? I tried to use Register 0X1B to adjust the phase relationship but there is no improvement. Such contaminated SYNC_CLK signals randomly happened for all the DDS chips after I reset the DDS chips and re-do the synchronization procedure.
3- The synchronization of multi-chips is depends on the phase-aligned SYNC_IN signals. Do the SYNC_IN signals need to present only during the calibration or they need to be provided all the time?
Any other suggestions and comments would be greatly appreciated.
Thanks in advance.