I've eliminated lots of spurs in the output of the AD9912 by driving it with a low noise 1 GHz osc, rather than
using the PLL. It works great!
Now, my SFDR is dominated and limited by a 50 MHz spur at -65 dBc. This is the serial data clock frequency.
The AD9912's FTW is being updated continuously, and I suspect that this data clock is somehow coupling to the output.
I am using the Analog Devices Eval board, Rev B.
Is there a spec for SCK feedthrough for the AD9912? I could not find one.
Perhaps the problem lies with poor PCB design and layout.
A little help?