We have successfully implemented the reference design. We would now like to give our own I and Q samples from our verilog module.
Can you just guide us on how to interface it with AD9122. We are using XPS and we do not have much experience with that.
From what i have gathered from other queries is instead of dma we need to send our own data.
if (C_DMA_BUS_WIDTH == 64) begin
dac_data_i0 <= dac_ddata[15: 0];
dac_data_i1 <= dac_ddata[15: 0];
dac_data_q0 <= dac_ddata[31:16];
dac_data_q1 <= dac_ddata[31:16];
dac_data_i2 <= dac_ddata[47:32];
dac_data_i3 <= dac_ddata[47:32];
dac_data_q2 <= dac_ddata[63:48];
dac_data_q3 <= dac_ddata[63:48];
This dac_ddata should come from our module.
We have 16 bit I and 16 bit Q samples.
So what are the steps we need to carry on in XPS to interface our module with axi_ad9122?