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ADIsimCLK (question about phase noise plot)

Question asked by brambakker on Jun 30, 2014
Latest reply on Jun 30, 2014 by Kyle.Slightom

Hi,

 

I have a question about the phase noise plot that is a result of the ADIsimCLK tool.

The plot consist out of 5 plot that show the phase noise of individual parts of the loop and one total.

 

Now my question is: Which noise is included in the chip plot?

Does this plot show only the pll noise (FOM) or also the noise added by the clk outputs?

 

thanks in advance for any answers.

 

kind regards

 

Bram

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