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AD9525 reference clock configuration

Question asked by Zartagal on Jun 27, 2014
Latest reply on Aug 11, 2014 by Kyle.Slightom


I'm currently working in the clocking design of a precision communication device with tight jitter requirements. For this reason, I decided to use the AD9525 chip, in order to get a total jitter around 100 fs.

Actually, I'm defining the reference clocks interfaces, and I have some questions. My idea is to use a local oscillator with very low phase noise in the input of the reference REFA. My target frequency is 2.112 GHz and I found a configuration with a 96 Mhz reference clock (ABLNO-96.000MHZ).

This is a LVCMOS clock supplied with 3.3V (REFA using only the possitive pin and ac grounding the negative pin). To increase the possibilities in the references, I decided to add another possibility of reference with an LVDS interface (REFB), an an external reference (REFC) through a connector.

I attach an scheme of the initial circuit for the reference system.


REFA: Used 50 Ohm external termination and ac-couplung. The input comes from the LVCMOS local oscillator.

QUESTION: Do I need this 50 Ohm external resistor for this input and 50 Ohm traces in this interface? Is it well defined?


REFB: LVDS input. 100 Ohm differential external resistor with ac-coupled capacitors.

QUESTION: Is this interface correct?


REFC: LVCMOS input. It comoes from a connector. In the datasheet says that it's not self biased and need external bias, but in the evaluation board datasheet appears with a dc-blockin capacitor and a 50 Ohm resistor.

QUESTION: What should I do, include the capacitor or remove it? Do I need here this 50 Ohm external matching impedance? Is this circuit correct?


Thanks a lot in advance!