One of my customer encountered a problem when they want to power up the HDMI sink through CEC. Would anyone could help on this issue? Thanks.
ADV7511 receives signal from FPGA and then send the HDMI signal to the first channel of AD8192. The pins of second channel on AD8192 are not connected. Then the outputs of AD8192 are connected to TPD12S016, an HDMI companion chip for ESD protection and level shift, as the application scheme on the datasheet of TPD12S016. The output of TPD12S016 is directed to the HDMI connector and then connected to an HDMI sink (TV).
Customer wants to power on the TV when HDMI cable is connected through CEC. The CEC_IO (pin 48) of ADV7511 connects with CEC_I/O (pin 53) of AD8192 through a 22.1 ohm resistor. The CEC_O/I (pin 46) of AD8192 is directly connected with CEC_A (pin
24) of TPD12S016. CEC_B (pin 6) of TPD12S016 is connected with HDMI connector. The CEC clock is around 18MHz and customer has set the CEC registers per CEC_clock_timing_register_calculator-ADV7511-family.xls in the design documents of ADV7511.
But the auto power on function cannot be realized. Customer had tried various ways and found if CEC pulled up through a 4.7k resistor to 3.3V, the problem can be solved. The pull up resistor can be put at the CEC_IO of ADV7511 or the CEC_O/I of AD8192. A 10pF cap to GND on one of these 2 pins also eases this problem.
Customer also found some weird wave occasionally appears on the CEC pin of HDMI connector as below.
Customer wants to know if the pull up resistor or 10pF cap is an effective solution to this problem? And if there's any solution that doesn't need hardware change?
I've found another potential issue about the logic level. The VCCA of TPD12S016 is 3.3V, so the VIL of CEC_A is -0.5 to 0.27V per the datasheet. While max value of the VOL of AD8192's CEC channel is 0.6V. Hence, the level on CEC_B of TPD12S016 is not defined if AD8192 outputs a 0.4V, which AD8192 considers low. I don't know whether this logic level mismatch can be a fatal mistake?