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Power-up/down Sequence Timing in Digital Potentiometers and Analog Switches

Question asked by dffdff on Jun 26, 2014
Latest reply on Jun 30, 2014 by dffdff

Hello.

 

I'm working on a project that includes dozens of the following devices: AD5260, AD5290, ADG1211, ADG1212, ADG1414.

I understand from their respective datasheets that voltage rails should be powered in a specific order: GND, Vdd/Vss, digital inputs and finally analog inputs/potentiometer terminals; power-down should be performed the other way around.

 

What is not so clear is how much time it is safe to have one rail powered before powering-up/down the next one, and if specific voltage levels should be reached on one rail before proceeding with the other rails.

 

Since so many devices are involved, and main power loss is a certain possibility (then relying on power source hold-up times to power down everything the safest way possible), I should time things very carefully, in particular on the power down sequence.

 

Also, there will be a considerable capacitive load involved, so it is important to know if power down of specific rails should be rushed in some way (activate dummy load or similar) in order to achieve the right timings during the sequence.

I would really appreciate your help in order to have the most specific information possible.

 

Thanks in advance to everyone.

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