Seeking support on customer issue with phase shift on IQ data when inputing sine wave that is offset from carrier. See below....
are doing some testing of the multi-chip synchronization features of the AD9361 chips. We have a board with 2 AD9361s on it that go into an FPGA and we are capturing RX data in the FPGA.
We have the data clock (and ADC clocks) synchronized as well as feeding in an external clock into the external TX and RX LO inputs.
I’m sending in a sine wave offset from the carrier. I’m seeing that within an AD9361 device the Port 1 and Port 2 IQ data is inverted (phase shifted by 180 degrees).
Is that to be expected?