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axi-dmac cyclic transfer + end of transfer interrupt question

Question asked by sbjaver on Jun 18, 2014
Latest reply on Jun 26, 2015 by larsc



This is hopefully an easy answer one way or another. Reading through the HDL for the AXI-DMAC, it appears that if i turn on cyclic mode transfer, there will never be an interrupt generated? So one would need to do polling on the software side to interact with an axi-dmac configured this way?


Or am i just misreading / no fully comprehending the verilog code?