I have a question about resistor divider value of AIN pin of ADV7182 with differential CVBS.Please see attached file "ADV7182_diff_CVBS_question".
Thank you.Best regards.
You have to look at the whole path from the source to Ain1. The source will be 2x signal amplitude with a 75 Ohm series resistor. The sink should be 75 Ohm so you get 1/2 the source amplitude from the resistor divider network. Then Ain needs a lower amplitude where the 650 Ohm resistor divide comes in. Two 650 resistors in series parallel to the 75 Ohm resistor will effect the sink loading a bit. Draw up and look at all 4 resistors in the path to figure out what the values should be.
Remember the cable is a 75 Ohm cable so the source needs a 75 Ohms series resistor and the sink needs to be 75 Ohms equivalent.
I believe making both resistors in the divider equal will accomplish what you want. May be 1.3k or 1k.
Thank you for your reply.
I think we have to consider impedance for transmitter side and clamp current from AIN pin when we determine the resistors.Is it OK both of 1.3k ohm or 1.0k ohm even if you consider them?
There is no current flowing out of the Ain1 pin. The 0.1 nF cap will block it.
If you want to keep the same impedance looking back from the Ain1 pin then both resistors would need to be ~650 Ohms, but I don't think this is an issue since Ain1 is a high impedance input.
I understand the maximum limit of the resistor is ~650ohm.How much is the minimum limit of the resistor?
Let me ask you an additional question.
I think the maximum limit of differential CVBS input is 4.0Vp-p.What voltage is the minimum limit?
What's important is what the pin voltages are. Normal pin single ended voltage will be 1.47Vpp * 51 / 75 = 1.0Vpp. In theory the connector voltage could be 100Vpp as long as you divide it down to the expected pin voltage of 1.0Vpp. If this voltage goes to low then you will not get peak colors and may start losing sync. If this voltage goes too high then you will start over driving the peaks.
The absolute peak analog input voltage is AVDD + 0.3V
What I want to know is the minimum limit of differential CVBS input.As long as I read your comment, at least I think 0.25Vpp input should be OK.What voltage is the minimum limit?
The ADC is expecting 1Vpp. Let me verify this with someone else.
The sync depth range = 20 - 200% of the nominal value. So if the nominal value is 1Vpp the device can handle 200mVpp at the pin and before the divider network the voltage would be 800mVpp, single ended.
For a full differential input the positive and negative input line would be 400mVpp
I can understand for case of single ended.Please let me ask you a question about full differential input.
About your following comment:>For a full differential input the positive and negative input line would be 400mVpp
Does the "400mVpp" mean minimum limit at the pin? or at the point before the divider network?
400mVpp on the connector, before the divider
I'm sorry many times.
Please let me confirm your comment.Please see attached file "single_end_and_differential.pptx".
checking with the expert again.
I start a new thread to discuss my last question.
Thank you!Best regards.
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