I have a AD1974 on a separate board that is configured by a microcontroller via SPI with the following values:
PCGA on the DSP is configured in the following way:
#define CLKA_DIVIDER 0x2 // used to create bit clock for ADC
// 24.576/2 = 12.288Mhz
#define FS_DIVIDER 0x80 // 24.576 / 128 = 192k
// for ADC bit clock and frame sync
// (1<<20) lines up FS with falling edge of BCLK
*pPCG_CTLA1 = CLKA_DIVIDER | (1<<20); // bclk divisor
*pPCG_CTLA0 = FS_DIVIDER | ENFSA | ENCLKA; // enable frame sync, enable clock, provide frame sync divider
*pPCG_PW = 0; // Pulse width 0 divides FS_DIVIDER in 2
*pPCG_SYNC = 0;
PCGA CLK (12.288MHz) is sent to the 1974 and SPORT0. PCGA FS (192kHz) is sent to the 1974 and SPORT0.
The SPORT is configured in the following way:
*pSPCTL0 = (OPMODE | SLEN24 | SPEN_A | SCHEN_A | SDEN_A |DTYPE1);
In summary, an ADC AD1974 is on a separate board and is set to derive it's PLL from the input LRCLK (192kHz), BCLK is 12.288Mhz, sample rate configured at 192kHz, operating mode I2S. Only one of the ADCs is being used and it is sending 24bit data to the SHARC, SPORT0A. SPORT0 is configured for I2S and 24bit data length. Both receive their clocks from a PCG.
When I inspect the SPORT DMA buffer, say a int, with a sinewave with an input frequency that is divisible by 200 (10000, 10200, 10400, etc) the data looks fine, it is as expected. However, when the input sinewave has a frequency not divisible by 200, even at 199, the data in the DMA buffer is immediatly corrupted. It looks as though there is a phase shift in the signal every so often, and in a pattern. I am assuming this is sampling gone wrong, and that somehow at frequencies divisible by 200 it just so happens that the corrupted signal looks like the original - just can't figure out why this is happening.
Attached is an example of the corrupted signal, dumped from memory.