I have set up a chained DMA transfer on the Sharc 21479 from SPORT1 to receive input data and have set up an interrupt after each block has completed.
When I run the code my interrupt function is called immediately after it completes even though no new interrupt has occurred yet.
After some searching in the hardware manual on interrupt control I found the following section:
There are three interrupt acknowledge mechanisms used in an ISR routine
and they depend on the peripheral:
• RTI instruction
• Read-only to-clear (ROC) status bit + RTI instruction
• Write-1-to clear (W1C) status bit + RTI instruction
The DAI/DPI interrupt controllers are designed such that in order to terminate
correctly, the latch register must be read to identify the source.
Note that this read automatically acknowledges the request before exiting
an interrupt routine. For the W1C mechanism, programs must write into
the specific bit of the latch register in order to terminate the interrupt
If the acknowledge mechanism rules are not followed correctly,
unwanted and sporadic interrupts will occur.
Now the questions:
1. Is a DMA interrupt considered as a DAI/DPI interrupt?
2. If so which register do I need to read to clear the interrupt in the DAI controller?
In the SPDIFToAnalogTalkThru(C) example code I do not see any such clear which make my confusion complete.