Im currently creating a project with adsp21489 in I2S, but I2s needs SCK,WS,SDA but as stated on the datasheet, DAI can be configured as simple GPIO(due to SRU will communiate to other peripherals), how can I connect it in I2S from other devices.
All you need to do is route the SPORT signals(CLK,FS,Data) to any of the DAI pins.and make then as input. The details of the SRU routing is given in the ADSP-214xx Hardware Reference Manual .But the easier way is to use the DAI Plugin for VDSP++ which gives the code for the required SRU routing. You can install the plugin by following the steps given in Application note EE-243 given in the following link.
thanks for the reply. for the I2S protocol you can only do it by 1:1 ratio per protocol. I also assume that this will be the implementation in the evaluation board as well as the application note you provided. here is my question:
1. How many IC with I2S protocol can I connect to the DAI pin including the CODEC ad1937?
2. is it possible for the ADSP21489 and I2S protocol to share same clock with other IC in order to maximize the I2S in the DAI pin?
I am the applications Engineer for the AD1937. This codec does not tri-state the unused slots in a TDM stream so you cannot share the same TDM data line. The clocks can be shared as long as there is enough drive strength and the signal integrity is taken care of. The AD1937 can be run in Daisy-Chain mode to add more data onto the TDM stream but not in stand-alone mode. I am fairly certain that this eval board is running the CODEC in stand-alone mode.
Hi Sir Dave,
thanks for the reply for AD1937. My AD1937 was just used for analog input/output signals. My concerns was the ADSP21489 if it can handle other all the IC's I2S whish include the Ad1937 in I2S protocol(to process the analog input signals)
ADSP-21489 has 8 SPORTs and 20DAI pins . So if all the SPORTs(configured in I2S mode) are Slaves, then each one of them requires 3 signals(CLK,FS,Data). A single DAI pin can be routed to many sources. So the Master CLK and FS can be routed to 2 DAI pins and these pins can be used to provide CLK and FS to all the SPORTs . Only the Data line of each SPORT has to be explicitly routed to different DAI pins.
In your case, all the ICs should have a synchronised CLK and FS if you have to share the CLK among all SPORTs.
thanks for the reply. then it should have a buffer for the CLK and FSY for signal integrity? I just want to confirm.
Thanks and Regards,
At the end of all, it should be made sure that the signal integrity is maintained.(with or without buffers).
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