I have few questions regarding FPGA Reference available on following link .
1. Which Xilinx JESD204B version is supported by this deign?
2. Can we configure different lane rates for JESD204B IP beside the deafult lane (6.25 Gbps) using this design?
3. Is there any Vivado based reference design for AD9250?
4. What is maximum lane rate supported by AD?