Does anybody know it or point where can I find a typical value of the rising edge duration of the SDCLK signal running 133MHz? I think I sought it everywhere...
Our data sheets do not provide the rising and falling edge duration. The timing for the peripherals including SDRAM provides the setup and hold times for data with respect to the clock. As long as the timing specs given in the data sheet are mainted it guarantees the proper functionality of the peripheral with respect to the DSP.
Hope this addresses your question.
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