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The hdl design of AD9361

Question asked by Andy_1 on Jun 12, 2014
Latest reply on Jun 23, 2014 by rejeesh

Hi,everyone. i have some confusions when i read the axi_ad9361 hdl design.I make a list as follows;

1.Can anybody briefly introduce the function about the submodule axi_ad9361_rx_pnmon, ad_datafmt, ad_dcfilter,ad_iqcor in the module axi_ad9361?

2.As for the submodule ad_dcfilter, it is not enabled? Because i did not see anything in the no os driver in the edk project:

void adc_init(void)

{

  adc_write(ADI_REG_RSTN, 0);

  adc_write(ADI_REG_RSTN, ADI_RSTN);

  adc_write(ADI_REG_CHAN_CNTRL(0),

  ADI_IQCOR_ENB | ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE | ADI_ENABLE);

  adc_write(ADI_REG_CHAN_CNTRL(1),

  ADI_IQCOR_ENB | ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE | ADI_ENABLE);

  adc_write(ADI_REG_CHAN_CNTRL(2),

  ADI_IQCOR_ENB | ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE | ADI_ENABLE);

  adc_write(ADI_REG_CHAN_CNTRL(3),

  ADI_IQCOR_ENB | ADI_FORMAT_SIGNEXT | ADI_FORMAT_ENABLE | ADI_ENABLE);

}.

3.As for the submodule axi_ad9361_tx_dds, i knew it was used to generator a Sin signal, and it was configured through the dac_core.c with the  relative command. but what is the frequency of each dds outputs,how to calculate their frequency?

4.When use the ad9361' design file included hdl and drivers,do i need some additional Settings or notes because ours design board uses the ad9364 chip?

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