On AD9361 for a given frequency offset, how do we arrive at the DCXO settings to be programmed into coarse and fine fields. Appreciate a pointer to this.
To use the DCXO, connect an external crystal (XO) between the XTALP and XTALN pins of the AD9361. Valid crystal resonant frequencies range from 19MHz to 50MHz. The crystal must be an AT cut fundamental mode of vibration with a load capacitance of 10pF.
By adjusting a capacitor within the AD9361, the resulting DCXO frequency can be adjusted to compensate for XO frequency tolerance and stability. Register 0x292[D5:D0] sets a coarse capacitor value while registers 0x293[D7:D0] and 0x294[D7:D3] set a fine capacitor value. Together, these three registers control the frequency of the DCXO. The resolution of the DCXO varies with coarse word with a worst case resolution (at coarse word = 0) of 0.0125 ppm. Using both coarse and fine words, the DCXO can vary the frequency over a ±60 ppm range.
Using a bench test, nominal DCXO trimming words in 0x292 through 0x294 should be determined and then used in an initialization script. These nominal words should be written before the AD9361 BBPLL is calibrated. After initialization (after the BBPLL and RFPLLs are programmed, calibrated, and locked), the DCXO words may be written at any time.
Are you using a crystal as a reference clock source?
Hi T lili
Yes, we use an external crystal and not a clock input.
Thanks T lili
In the same manual, we have the expression
Capacitance = 200fF * DCXO Tune Coarse <5:0> + 0.5fF * DCXO Tune fine <12:0> . . .Equation 59
For a given frequency offset, is there a calculator to obtain Capacitance and thereby calculate the register settings or does it have to be a bench test (trial and error) method.
The expression will give you capacitance vs tune word. The capacitance you arrive at will pull crystal frequency and that is a function of the crystal being used. I think that you will most likely have to determine Hz/tune empirically on the bench. It most likely will not be linear.
Retrieving data ...