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Having trouble operating AD7191 device...

Question asked by ChungminH on Jun 10, 2014
Latest reply on Jun 24, 2014 by ChungminH

Hello I am Chungmin Han, currently a graduate student in Seoul National University, South Korea.

I am developing a simple pcb using AD7191 to acquire bio-signals and facing several problems so I was hoping I could get

some advice on this. (fascinated how delicate the chip converted with high resolutions, I was informed to use this chip.)


I checked how bio-signals(like ECG) appeared by first acquiring through AD7191 Evaluation Board,

However, I need circuit that transmits data wireless so I used ATmega128 for MCU, bluetooth and

power regulators that we used frequently, but the circuit is not stably working and I can't seem to find out what the problems are.

The descriptions below is value I assigned to the AD7191 chip.

1 - MCLK : We used internal clock source 4.92MHz so Not Connected

2 - MCLK : same as pin1 Not Connected

3 - SCLK : The Pulse for reading ADC result bit is generated from ATmega128 as High-Low sequence 24 times when RDY is down

4 - PDOWN : is tied to GND (Logic 0)

5 - CLKSEL : is tied to DVDD (Logic 1) to use internal Clock 4.92MHz

6, 7 PGA : are tied to output of ATmega128 parallel I/O port with pull-up register (to select either 0, 1)

8 - CHSEL : is tied to output of ATmega128 parallel I/O port with pull-up register (to select either 0, 1)--> we selected AIN3,4 this time

9 - TEMP : is tied to GND (we are not using temperature correction)

10 - NC, tied to GND

11, 12  AIN 1,2

13, 14  AIN 3,4

15, 16  REF +, - : we tied REF+ to half of AVDD and - to GND

17, 18, 19 AGND, DGND : we died altogether

20 AVDD : we tied AVDD to 5V from output of regulator LT1763-5 with 10uF tantal capacitor

21 DVDD : we tied DVDD to 3.3V from output of regulator LT1763-3.3 with 10uF tantal capacitor

22, 24 ODR : are tied to output of ATmega128 parallel I/O port with pull-up register (to select either 0, 1)

23 DOUT/RDY : the output of this pin is connected to one of ATmega128 parallel I/O as input (we are monitoring only one bit)

Power regulator is coupled with appropriate tantal capacitor, and Output logic of ATmega128 is 3.3V(High) and 0V(Low)

The circuit is composed of ATmega128, AD7191, Power regulator(LT1763-3.3, 1763-5), ISP pin, Bluetooth for data transmission, and that's all. (It is also denoted in design & circuit I attached below)


I'm having several problems


1. The chip works only when I literally 'touch' the AIN3 pin (I first assumed it was a connection problem and switched the chip or change the wire, but it did not work). When AIN3 touched, with ODR set to be 120, I checked that RDY value went down every 8.33ms(1/120) and pulse generated from ATmega128 that goes into SCLK when RDY ready also clean.


2. The signal we received (while I am touching the AIN3 pin) had major amount of noise, the waveform looked as if it was amplitude modulated, I understand that in 120 Data rate mode, the 60Hz notch is not provided (mentioned in data sheet) thus I checked that power around 60Hz was very dominant. But still after band-pass filtering the signal, the desired ECG did not appear.... The input signal is voltage value.


Is there anything that I am missing to operate AD7191 properly? Any kind of advice or skeptical points would be much of a help.

(So to speak frankly, this is my first time working on hardware design, so I do not have general sense of dealing with chips or circuits, not in real situation though I majored electrical engineering.)


Thank you


Chungmin Han


ad7191 chip.jpg사본 -Breadboard.jpgSCLK Pulse22.jpg