I'm testing the performance of the AD9789 in the chanelizer configuration.
I have the Eval Board of the chip connected to one FPGA Xilinx Virtex6 with an LVDS interface for control and data signals. The program in the FPGA is very simple, it generates a Fs/4 signal that sends a sample for every pulse in the FS control signal from the AD9789.
I want to check how the Sample Rate Converter in the AD9789 works when I change the configuration of the P and Q registers of this block of the chip.
First of all, I have tuned the data interface with the instructions in the datasheet for the calculation of the Latency, DSCPHZ and SNCPHZ, but the values calculated I've found doesn't match the values required for the chip to works properly. The value of the Latency register needs to be changed when I change the number of Interpolation filters I've been using and the values for the DSCPHZ and SNCPHZ registers can be set in a random values with no impact in the output of the DAC. I've configured the data interface to check integrity of the data in the IQ parity configuration and there is no error reported by the chip.
What I really want is to check the AD9789 Sample Rate Converter behavior and for that, I program different values for the P and Q registers. The result I have obtained for different values in this registers are unpredictable. For example, if I program P = 0x800000 and Q= 0x800000, the output signal is OK, the tone appears at FS/4 as it should. The same result is obtained if P = 0x400000 and Q = 0x800000 or P = 0xB1A000 and Q = 0xC80000 (Example in the Datasheet page 42). But, when I program P= 0xA1A000 and Q = C80000, in the output of the DAC appears plenty of spurs in the band of the BPF of the last stage 16x Interpolation filter. The restrictions in the Datasheet for P and Q are still OK, Q = 1 and 0.5 < P/Q < 1, but the output is not.
There is more restrictions for the P and Q calculations? , should I check the configuration of other parameters in the chip?, There are something I could be doing wrong in the configuration of the chip?