I am working on a FRAC-N synthesizer design using an ADF4351. The intention is to cover a wide range of output frequencies with a 1KHz RF output resolution.
Although the output appears to go to the correct frequency neither the dedicated LOCK pin nor the MUXOUT when configured for Digital Lock Detect goes high. The behavior is the same from 200MHz to 4.4Ghz although I have only selected a few dozen test frequencies. I am not watching the output phase so the phase could very well be out of lock.
I thought I was successful in validating the loop dynamics using ADISim but obviously I am missing something fundamental. The loop appeared to lock from power up to 4.4GHz and for various steps in under 60us. I used the Digital Lock Detect as the metric.
The REF input is 10.000MHz and the R-Counter is set to 10 with no doubler or divider set. This gives the Fpfd =1MHz.
CP set 8 for about 2.7mA
The MOD is set to 1000 to give a 1KHz RF output resolution.
The loop filter was designed for a BW=100KHz at a 45deg phase margin
Band Select Clock mode = high
Band Select Clock divider set to 4 to divide 1MHz Fpfd to 250KHz which means 10 Pfd cycles requires 40us
Clock Divider = 1
FastLock is enabled with timer divider of 1 set
Cycle Slip Reduction s disabled
Low-spur mode ON
In an effort to debug the problem, I set the MUXOUT to monitor the R counter (3) and that appears to be operating at the desired Fpfd of 1MHz. However, when I set the MUXOUT to monitor the N Counter (4) the output frequency becomes unstable and is far from the target frequency. What does this symptom indicate?
With MUXOUT configured for the analog lock detect, I get a sawtooth (more like an exponential) at the Fpfd rate that varies between 2V and 4V.
If I am missing any other critical register setting please advise as to lack of LOCK assertion and why the loop becomes completely unstable when MUXOUT set to N-Counter.
Any guidance would be appreciated,