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XTAL_FREQ_SEL of ADV7619

Question asked by Kikka on Jun 9, 2014
Latest reply on Jun 12, 2014 by Kikka

Hello.

 

When a particular equipment that pixel clock varies slightly per frame is used as source, Hsync and DE output become unstable.

(Vsync remains stable).

 

But I tried to change the value of XTAL_FREQ_SEL(IO map, 0x04[2:1]), then Hsync and DE output would be stable.

 

XTAL_FREQ_SEL= 00b ----- NG

XTAL_FREQ_SEL= 01b ----- NG

XTAL_FREQ_SEL= 10b ----- OK

XTAL_FREQ_SEL= 11b ----- OK

(we use 28.63636 MHz crystal)

 

Would you tell me what changing the XTAL_FREQ_SEL register makes any effect to internal of ADV7619?

And are there any side effect?

 

Best regards.

Kikka

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