1 supply current of ad9958 is 60mA lessthan the datasheet' value 60+90=150mA.
2 programing the reference divide ratio N=19,but SYN_CLK output always 6.5MHz one fouth the referece freq 26MHz,it seems that the
PLL in IC is not on work.
I am not sure I understand the problem, are you actually getting any output frequency from the DDS? Is it a custom board?
If you are getting SYNC_CLK at 1/4 the reference frequency it seems like the chip is working properly. Maybe you just have a problem programming it. One trick I tried when I had problems with clock and communications on this chip is to send the command to disable SYNC_CLK and see if it turns off.
The current draw changes depending on if it is outputting signal or not so I don't think that means anything. Current draw also drops very low if you hold the reset line high.
this post seems to be a bit longer and overlooked.
Can you tell me what is the setting of your AD9958? The current consumption is dependent on what DDS blocks are used.
SYNC_CLK for AD9958 is 1/4 the system clock. In your case, if your SYSCLK is 26MHz, then the SYNC_CLK output you are seeing is good.
Let us know if this post has been resolved already.
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