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Reg. operation of (DREADY & 12-bit counter) and usage of ADC_NA bit in STATUS1 in  ADE7913

Question asked by vipul on Jun 9, 2014
Latest reply on Jun 9, 2014 by dlath


I am using ADE7913. It is having crystal of 4.096 MHz (according to device datasheet).

ADC is operating at 4.096 / 4 = 1.024 MHz (or ADC-clk period is 0.9765 us).

ADC output frequency is configured 8 KHz (i.e.12-bit counter possess 512'd). i.e. Every 125 us, ADC outputs all 3-channels - each 24-bit result data and stores them into their respective result registers.


Well, i don;t know at this stage, the acquisition time and conversion time. Obviously, that would have been taken care in IC. ADC output frequency is sufficient to resolve ADC timing related queries.


I have few more below queries. Please provide your understanding.

1. Whenever ADC operating period starts, DREADY signal is active low for 64 CLKIN (i.e.15.625 us).

    Query_1: Does it mean that ADC result read operation has to be started and completed within this 15.625 us or has to be started within 15.625 us but has to be completed within one ADC output period?

    Query_2: Will i be not able to read the ADC result when DREADY is not active low?

2. Whenever ADC result is not read within one ADC output period i.e. 125 us, then ADC_NA bit is SET in STATUS1 register.

    Query_3: Does it mean that if i miss to read the ADC result within one ADC output period & if i attempt to read in next active low of DREADY, then does ADC will give new conversion results or will wait till i read STATUS1 register for ADC_NA bit to become zero?

3. If i attempt to read the same result register - will i be getting the same result or unknown value?


If anyone knows this then let me know. This will assist me in designing my HOST-side code-design.