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BF607 SMC Timing

Question asked by livio on Jun 8, 2014
Latest reply on Jul 2, 2014 by VineethaThomas

Hi,

I'm confused about processor's signal AMSx (SMC chip select)

I initialise processor (CLKIN = 32M) as

<register-reset-definitions>

  <!-- Init clocks( CCLK = 496 Mhz, SCLK = 250Mhz, SCLK0 = 125Mhz -->

  <register name="CGU0_CLKOUTSEL" reset-value="3" core="Common" />

  <register name="CGU0_DIV" reset-value="0x01024241" core="Common" />

  <register name="CGU0_CTL" reset-value="0x00001f01" core="Common" />

 

then, in the code, SMC is initialized as:

*pREG_SMC0_B1TIM = 0x01110402;        // Access Time
*pREG_SMC0_B1ETIM= 0x00020100;        // Access Time (ext)
*pREG_SMC0_B1CTL= 0x001;              // Start Module

 

now I'm expecting that, when executing a read in AMS1 domain, the cycle lenght is 3 cycles of (1/124MHz) = 8.065nS*3 = rroughly 25nS.

Instead I measure roughly 380nS, which is an enormous time.

Where I'm wrong?

Thanks...

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