AnsweredAssumed Answered

LO Design Low SSB Phase noise DC to 100MHz

Question asked by rjrodrig on Aug 19, 2010
Latest reply on Aug 20, 2010 by DSB

Hello,

 

I am trying to implement a low SSB phase noise tunable signal generator to be used as LO iin a larger system.  The entire system should better than say -134dBc/Hz @ 20KHz which are the specs of an agilent E44XX sigGen I am using now.  They claim the phase noise @ 500MHz is < -135dBC/Hz @ 20KHz offset.  Using this instrument we seems to do well with the instruments we have and I am trying to create a custom setup to rid of the agilent and other big equipment out of the way.

 

I NEED HELP ON THIS:


The frequency ranges I care are say 1MHz up to 100MHz.  Resolution is important in order to tune the LO to the correct frequency to produce a precisise frequency beat.

 

I have very precise reference clock say 0.1ppm or Better @ 10MHz or 75ppb @ 10MHz.  I could use these a the time base for the systems.  The issue is that I can feed a 100MHz clock with 0.5ppm into the DDS, but I was told by an application engineer at Analog, I can only go up to Fref/2.  I would be short reaching only 50MHz.

 

How can I design an LO tunable from DC up to 100MHz with low phase noise never worse than 134 dBc/Hz when the frequency is 100MHz?

 

What DDS ADI models parts do I need? doesn any one know?

 

I have seen so many models, and I am not sure what to pick.  I need to educate myself on the effects of the phase noise.  Is it additive, or does it multiply.  For example, I have a Reference clock, a PLL and a VCXO to generate 200MHz to be fed into a DDS.  The Reference clock has an excellent jitter number something like 0.1psec RMS, the PLL has a residual phase noise, and the VCXO another.  How do I perform an analysis to know the effective phase noise of the system?  Is just like adding phase noises like A + B + C where A = Ref Clock, B=PLL, C=VCXO.  Then this output drives the DDS to be able to tune the output frequency from DC to 100MHz.  What is the resulting phase noise then?  I don't want to build the system and then measure it and realize is no good.

 

What DDS model number do I need from Analog devices?
What model PLL do I need?

 

I know you will suggest go talk to an apps engineer, I did, the guy could not answer any questions, other than just providing me some models, and in my mind he just gave me part numbers than go up to 1GHz to broaden the design specs.  I think that would just degrade the phase noise since the PLL needs to multiply 10MHz up to a GHz.  I don't think this is the correct approach.

 

DDS on the other hand reduces phase noise due to oversampling and dividing.  So I am wondering if RefCLK + PLL + DDS = tunable LO with low phase noise.

 

BTW the -134 dBc/Hz is the spec of an Agilent E4XXX instrument we use now as LO.  I am just trying to simplify the instrumentation by getting rid of the Agilent and putting a reference oscillator (tunable) in the design.

 

Can someone Guide me as to what to do?

Attachments

Outcomes