What is the recommended sequence to configure the clock rate for the core to 80MHz?
By default the part starts up with a core clock of 80MHz and a PCLK of 20MHz for the peripherals.
You can slow down the core clock rate by writing to the CLKCON1 register. The only precaution to take is to make sure that you don't set PCLK greater than the core clock (HCLK)
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