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KC705+FMCOMMS2(AD9361) build vivado project with HDL reference design, some input pin are unconnected!

Question asked by w9001156 on Jun 5, 2014
Latest reply on Jun 9, 2014 by rejeesh

I am using KC705+FMCOMMS2 to do test with AD9361. After I download HDL reference design and build project with vivado.

After P&R is done, it is reporting the following un-connected input pins for some IP. and I check the RTL file, finally vivado auto-connect the following signals to "GND_1".

My Question is: Does this behavior expect? or did I missing something?

 

[BD 41-759] The input pins (listed below) are either not connected or do not have a source port, and they don't have a tie-off specified.
Please check your design and connect them if needed:
/axi_ddr_cntrl/device_temp_i
/axi_hdmi_dma/mm2s_frame_ptr_in
/sys_audio_clkgen/reset
/axi_ad9361/dac_enable_in
/axi_ad9361/adc_dunf
/axi_ad9361/dac_dovf

 

Please help, thank you.

May

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