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Understanding iio_oscilloscope and cf_ad9361_zed

Question asked by on Jun 4, 2014
Latest reply on Jun 4, 2014 by mhennerich


I have a question about the structure of iio_oscilloscope and the communication chain from the software application to the FMCOMMS2 device. I am writing my own digital baseband application to interface with the DAC/ADC with its own registers, and want to write my own software driver to control this core.


I am trying to understanding the chain of how the various UI knobs to read/write various properties get translated to low level commands either to the baseband core (e.g. read/write DDS scale factor, write I-Q samples to DAC) or to the FMCOMMS2 device itself (e.g. read/write sampling frequency, center frequency etc.) I am particularly interested in the full chain (from application -> Linux device driver -> Xilinx XPS -> hardware) of how the logical names actually get translated to actual register read/write instructions.


For instance, I see that the enable_dds(...) function in plugins/fmcomms2.c in iio-oscilloscope makes calls as follows:


       write_devattr_int("out_altvoltage0_TX1_I_F1_raw", on_off ? 1 : 0);

        if (on_off || dac_data_loaded) {

                ret = write_devattr_int("buffer/enable", !on_off);



Following the implementation of write_devattr_int(...) in iio_utils.c, I see that it calls write_devattr(...) which in turn calls write_sysfs_string (or similarly, read_devattr(...) calls read_sysfs_string).


How are these writes and reads to these magic names in sysfs translated to actual reads/writes connected to the verilog/actual FMCOMMS2?


Apologies if this question is too simplistic, but I would really appreciate your walking me through this so that I can extend/build my own baseband/software applications for this device.





P.S: As far as I can tell, IIO Oscilloscope does not use libiio. If I should use and extend libiio as a solution going forward, I would appreciate if you can explain this same question in the context of libiio instead. Also, if I should post this question in the "FPGA Reference Designs" in order to understand the hardware side of the mapping chain, please let me know and I will do so.