AnsweredAssumed Answered

AD9129 start up sequence

Question asked by HWNUM_MAN on Jun 4, 2014
Latest reply on Jun 4, 2014 by danf


We  use a DAC AD9129 on a board  with a frequency sample (DACCLK) from a PLL ADF4350. We do the "startu up sequence" with a FPGA.

with a frequency sample 2412Mhz, The PLL internal AD9129 is locked after the "startup sequence".

with a frequency sample 1608Mhz, The PLL internal AD9129 is NOT locked after the same "startup sequence".


The levels and SFDR of theses fréquencies are good. Common Mode Voltage on DACCLKs pin (P and N) is good (1V2).


We don't understand why the AD9129 is not locked on 1608Mhz!


has someone a idea ?


Here is our "strart up sequence"


Séquence de start up (in yellow  différences with data sheet)

0 => (x"00", x"00"),    -- 4-wire PSI, MSB-first packing, short addressing mode

1     => (x"30", x"5C"),    -- Enable cross control, cross location=7, duty cycle correction off

2     => (x"0C", x"64"),    -- Set DLL minimum delay=4, enable DCO

3     => (x"0B", x"39"),    -- Set clock divider to DCI/512

4     => (x"01", x"68"),    -- Set bias power-down

5     => (x"34", x"6D"),    -- Set PLL mode for normal mode

6     => (x"01", x"48"),    -- Enable bias

7     => (x"33", x"17"),    -- Initialize PLL to phase step=1 , DCO divider=4

8     => (x"33", x"FC"),    -- Select PFD, Se PLL phase step, keep PLL lost bit cleared

9      => (x"33", x"F4"),    -- Deassert the PLL lost bit, keeping the phase step

10     => (x"0D", x"06"),    -- Set duty correction bandwidth to lowest

11     => (x"0A", x"CC"),    -- Enable DLL, phase offset = -4

12     => (x"18", x"00"),    -- Select data mode

13     => (x"20", x"C6"),    -- Set full-scale current (FSC) to 33 mA

14     => (x"21", x"03"), -- Complete the setting of FSC

15     => (x"30", x"46"),    -- Enable cross control, cross location=1, enbale duty cycle correction

16     => (x"12", x"20"),    -- Set the FIFO pointers

17     => (x"11", x"81"),    -- Assert FIFO reset

18     => (x"11", x"01"),    -- Deassert FIFO reset

19     => (x"01", x"08"),    -- Enable Iref (DAC output)