I am using an AD9608BCPZ-125 ADC. I would like to operate in both "INTERLEAVED PARALLEL LVDS " & "PARALLEL CMOS" modes.I have connected all the required pins to FPGA for operating it in both modes.
I have some doubts,
In "PARALLEL CMOS" mode pins 25, 26 etc., are NC, but in "INTERLEAVED PARALLEL LVDS " mode they act as Clock and Data.
So when I am using it in "PARALLEL CMOS" what level ( VCC or GND or High-Impedance ) should I have to maintain on these pins ( 25,26.., )
Its very URGENT, expecting your reply ASAP.