After updating all the Xilinx cores to the latest versions so the fmcomms1 for zc702 AD9643 board would compile, I now get the following error, and am struggling to fix it. Please advise... Paul...
CRITICAL WARNING: [Timing 38-249] Generated clock inst/i_mmcm_drp/mmcm_clk_0_s has no logical paths from master clock clk_fpga_1.
Resolution: Review the path between the master clock and the generated clock with the schematic viewer and correct the -source option. If it is correct and the master clock does not have a timing path to the generated clock, define the generated clock as a primary clock by using create_clock.
WARNING: [Timing 38-164] This design has multiple clocks. Inter clock paths are considered valid unless explicitly excluded by timing constraints such as set_clock_groups or set_false_path.
ERROR: Timing Constraints NOT met.