I'm using AD9837 as an OOK (on-off keying) modulator on a prototype board.
The DDS is driven by an Altera Cyclone IV FPGA providing MCLK (15.6MHz) ,SCLK (4MHz),FSYNC and SDATA.
On the output side we're driving a non-inverting op-amp amplifier, which is used as a pre-amplifier.
Sometimes, it seems that the DDS ignores the command I send from the FPGA.
off keying modulator, I've initialized the DDS using the following command sequence, then I switch FSEL whenever I've a transition between 0 and 1. This is my init. sequence:
For switching FSEL, I use 0x0000 (f0) or 0x0800(f1).
In the attached image tek00109, you can see that our command (0x0800) respects all timing requirements.
On the upper slot of the image, you can also see that after this command (marked with the gray cursor) the output of the DDS still generates a 152kHz sine wave (Yellow trace).
On the other hand, in image tek00112 you can see that the same command forces the DDS to stop the output wave (see gray cursor on the upper slot).
I've verified all timing requirements in the datasheet, I've tried to reduce the SPI frequency and I also tried to give many times the same command for each transition in the output data flow, but I didn't solve the problem.
The only thing I noticed is that the error is more frequent at the maximum SPI frequency, even though the timing requirements are always respected.
I assume the DDS is the only responsible for this problem.
Please, could You provide a feedback about a possible cause of this behaviour?