AD9915 datasheet feature request: PLL loop bandwidth

Discussion created by MvdMerwe on May 29, 2014



We are using the AD9915 in a design, and are using the internal PLL for the first time. We found out a bit too late that we can't decrease the loop bandwidth as much as we would have liked and I want to make a few suggestions that will make the datasheet a bit more user-friendly in this regard.


On p.22 of the datasheet (Rev. D) information is given about the possible charge pump current settings, and one example is given of what the loop bandwidth would be under certain conditions. It would be helpful it there was an equation for calculating the loop bandwidth, given the value of Icp and N, instead of having to scale it from the given example.


Also, the phase noise graph on p.14 (Figure 19) would be more helpful if the relevant system parameters were provided in the caption (e.g. Ref Clk frequency, Icp, N).


I am hoping that some other users will find these clarifications useful as well.