I think i know the answer to this, but I'm hoping I'm wrong.
I have a customer that needs to generate a PWM output with <= 100 nsec. resolution. If I read the User's guide correctly, the ADuCM361 must divide UCLK by 2 minimum. At 16 MHz, this yields a PWM resolution of > 100 nsec.
Is there anyway to bypass the UCLK divide into the PWM module? Is there another way to generate a higher resolution PWM with the 361? Other than this deficiency, the ADuCM361 looks to be an excellent fit.